Carrier board design-in training
Everything you need to know for a head-start in carrier board designs
Carrier Board Design-in Training
Scope?
This course provides in-depth training on all carrier board-related design topics. The focus is on the design-in of COM-HPC and SMARC Computer-on-Modules.
Target Audience?
Carrier Board Hardware Design Engineers
Price
500 USD per person
When
Online
| May 19th - 22nd 2025 | (Monday – Friday, each from 9 am – 12 pm PST) | US |
| October 20th - 24th 2025 | (Monday – Friday, each from 9 am – 12 pm CET) | EMEA / APAC |
In-person
| October 14th - 15th 2025 | (Tuesday + Wednesday, each from 9 am – 5 pm CET) |
Agenda
- Introduction Carrier Board Design
- COM-HPC Update
- High-speed Standard PC Interfaces (e. g. PCIe, USB, Ethernet, Displays)
- Low-speed Standard PC Interfaces (e. g. eSPI, I²C, GPIOs)
- Power Management
- Design Basics & Carrier Board Component Selection
- PCB Design Rules
- Signal Integrity in Embedded Applications
- congatec x86 Firmware (e. g. Embedded BIOS and Board Controller Features)
- Carrier Board Design Verification Test and Mass Production Tester
- Cooling Concepts
- Design-In Support incl. Roadmap Update and TSC Services
Register for training
Learn more about Computer-on-Modules
Computer-on-Module standards
A lot is happening in the Computer-on-Module market today. With SMARC 2.1, a new version of the low-power module specification is now available. And COM-HPC, the soon-to-come high-end embedded computing standard, is also raising many new questions. So what do OEMs and system designers need to know?
Download Technical Article
